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Central Processor Unit (CPU) Registers
Table 4-3. Operating Mode Register (OMR) Bit Definitions
Bit Number
23
22–21
Bit Name
MSW[1–0]
Reset Value
0
0
Description
Reserved. Write to 0 for future compatibility.
Memory Switch Mode Bits 1, 0
When enabled by the MS bit 7, the two bits configure the internal memory
sizes for Program, X-data, and Y-data memory. See Chapter 3 for details.
Notes: 1.
2.
To ensure proper operation, place six NOP instructions after
the instruction changing the MS bit.
To ensure proper operation, do not change the MS bit while
the Instruction Cache is enabled (SR[CE] bit is set).
20
SEN
0
Stack Extension Enable
Enables/disables the stack extension in data memory. If the SEN bit is set,
the extension is enabled. Hardware reset clears this bit, so the default out
of reset is a disabled stack extension.
19
WRP
0
Stack Extension Wrap Flag
Set when copying from the on-chip hardware stack (System Stack
Register file) to the stack extension memory begins. You can use this flag
during the debugging phase of the software development to evaluate and
increase the speed of software-implemented algorithms. The WRP flag is
a sticky bit (that is, cleared only by hardware reset or by an explicit
MOVEC operation to the OMR).
18
EOV
0
Stack Extension Overflow Flag
Set when a stack overflow occurs in Stack Extended mode. Extended
stack overflow is recognized when a push operation is requested while SP
= SZ (Stack Size register), and the Extended mode is enabled by the SEN
bit. The EOV flag is a sticky bit (that is, cleared only by hardware reset or
by an explicit MOVEC operation to the OMR). The transition of the EOV
flag from zero to one causes a Priority Level 3 (Non-maskable) stack error
exception.
17
EUN
0
Stack Extension Underflow Flag
Set when a stack underflow occurs in Extended Stack mode. Extended
stack underflow is recognized when a pull operation is requested, SP = 0,
and the SEN bit enables Extended mode. The EUN flag is a sticky bit (that
is, cleared only by hardware reset or by an explicit MOVEC operation to
the OMR). Transition of the EUN flag from zero to one causes a Priority
Level 3 (Non-maskable) stack error exception.
Note:
While the chip is in Extended Stack mode, the UF bit in the SP
acts like a normal counter bit.
16
XYS
0
Stack Extension XY Select
Determines whether the stack extension is mapped onto X or Y memory
space. If the bit is clear, then the stack extension is mapped onto the X
memory space. If the XYS bit is set, the stack extension is mapped to the
Y memory space.
15
ATE
0
Address Trace Enable
This bit is valid if the operating frequency is 100 MHz or less. When the
conditions are valid and the bit is set, the Address Trace Enable (ATE) bit
enables Address Trace mode. The Address Trace mode is a debugging
tool that reflects internal memory accesses on the external address bus.
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
4-11
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